A tuning circuit (resonance circuit) of the electronic tuning type frequently uses a variable capacitance diode. However, where a variable capacitance diode is used, since a high bias voltage is required, for example, such a variable capacitance circuit as shown in FIG. 9 has been proposed.
In particular, in this circuit, when the bit bi (i=0 to n) of digital data has the “H” level, since a corresponding MOS-FET (Qi) is on, a capacitor Ci connected in series to the FET (Qi) is connected between a terminal T1 and another terminal T0. However, when the bit bi has the “L” level, since the corresponding FET (Qi) is off, the capacitor Ci is not connected.
According, if the capacitor Ci is set toCi=C0×2 to the (n+1)th powerthen the capacitance CVR between the terminal T1 and the terminal T0 can be varied among a number of values equal to 2 to the (n+1)th power by a step of the value C0 betweenCVR=0 and C0×(2 to the (n+1)th power−1)with respect to the level of the bits b0 to bn.
In particular, the circuit of A of FIG. 9 is represented as such an equivalent circuit as shown in B of FIG. 9 and is a variable capacitance circuit whose capacitance can be varied with the bits b0 to bn. It is to be noted that, in B of FIG. 9, resistance r is on-resistance of the FET (Qi), and capacitance CS is floating capacitance.
Meanwhile, also such a circuit as shown in FIG. 10 has been proposed as a variable capacitance circuit. In particular, in the circuit of FIG. 10, a bias voltage +VDD is supplied to the drain of an FET (Qi) through a pull-up resistor Ri. And, also in this circuit, since the FET (Qi) is turned on and off with the bits bi of digital data for controlling similarly to the circuit of A of FIG. 9, variable capacitance CVR can be obtained between a terminal T1 and a terminal T0.
And, since those variable capacitance circuits do not require such a high bias voltage as in the case of a variable capacitance diode, they are advantageous in integration (Official Gazette of Japanese Patent Laid-Open No. 2005-287009, Official Gazette of Japanese Patent Laid-Open No. 2006-080620).
However, in the variable capacitance circuit shown in A of FIG. 9, a parasitic diode DPR is produced between the drain and the back gate originating from the structure of the FET (Qi) as shown in C of FIG. 9, and a series circuit of this parasitic diode DPR and the original capacitor Ci is connected between the terminal T1 and the terminal T0.
When the FET (Qi) is on, the parasitic diode DPR does not matter very much because it is shunted by the on resistance r of the FET (Qi).
However, when the FET (Qi) is off, if the amplitude of an input signal supplied between the terminal T1 and the terminal T0 exceeds 0.5 Vp, then the parasitic diode DPR is turned on and the input signal is rectified by the parasitic diode DPR. Therefore, a dc potential difference appears between the drain and the source of the FET (Qi). And, this dc potential difference varies in accordance with the amplitude of the input signal.
As a result, the equivalent capacitance of the parasitic diode DPR varies in accordance with the input signal, and at this time, since the parasitic diode DPR is connected to the terminal T1 through the capacitor Ci, the total capacitance CVR between the terminal T1 and the terminal T0 varies in response to the input signal.
Further, even if such a high input signal as described above is not applied, since the dc potential difference applied across the parasitic diode DPR is 0 V, the junction capacitance of the parasitic diode CPR is comparatively high. And, the signal voltage (input signal) is applied to the parasitic diode DPR through the capacitor Ci. As a result, the junction capacitance of the parasitic diode DPR is varied by the applied signal voltage, and the variation width is great. Besides, the capacitance variation occurs in a region in which the nonlinearity of the capacitance is great.
Accordingly, in the circuit of A of FIG. 9, distortion to the input signal is great, and if the circuit is used, for example, in a tuning circuit of a receiver, then since a disturbance signal component is produced by the distortion, a strong reception signal cannot be handled.
Meanwhile, in the variable capacitance circuit of FIG. 10, even if the parasitic diode DPR is produced, since the parasitic diode DPR is reversely biased through the resistor Ri, if the reverse bias voltage +VDD is set to a high level, then the junction capacitance of the parasitic diode DPR becomes low and also the variation of the junction capacitance with respect to the input signal becomes small. Accordingly, appearance of distortion can be suppressed.
However, in the case of the circuit of FIG. 10, when the FET (Qi) is on, current flows through the resistor Ri with the bias voltage +VDD. Besides, the (n+1) resistors Ri are provided. Accordingly, it is necessary to reduce the current to flow through the resistor Ri. To this end, it is necessary to set the resistance of the resistor Ri to a high value such as, for example, several hundreds kΩ, and where the circuit is integrated, the area occupied by the resistor Ri becomes great, which is not favorable.
The present invention contemplates solution to such problems as described above.